1. Field of the Invention
The invention is directed to single crystal substrates having a heteroepitaxial layer deposited thereon, and to a process for producing wafers having an epitaxially deposited heteroepitaxial layer thereon.
2. Description of the Related Art
A crystalline heteroepitaxial layer deposited on a single crystal substrate by epitaxial deposition typically differs from the substrate in several material properties including crystal lattice dimensions and thermal expansion coefficient. During the early stages of the deposition the heteroepitaxial layer is strained with respect to the underlying substrate lattice. After exceeding a certain layer thickness (critical thickness), the crystal of the heteroepitaxial layer starts to relax via the insertion of so called misfit dislocations (MFD). Although oriented in a plane perpendicular to the growth direction, not all MFD extend to the edge of the substrate wafer, but rather a certain number bend and form threading dislocations (TD) propagating through the growing layer to the surface. TD forming clusters along lines are called pile-ups (Pu) and are especially harmful for electronic devices. The stress fields from the dislocation network also cause a surface roughening called cross-hatch. The formation of MFD, Pu, TD, cross-hatch and a bending of the wafer (bow, warp) are mechanisms by which the strain from the lattice mismatch is relieved.
Many epitaxial deposition techniques have been developed to reduce the negative effects of the strain relaxation on the crystal quality of the heteroepitaxial layer. SiGe deposition on Si is a well known system to increase the lattice constant from Si to pure Ge which has a lattice constant being 4.2% larger than that of Si. Grading of the Ge concentration in the SiGe layer has been a successful way to reduce the density of TD and Pu and the surface roughness of SiGe buffer layers. Many variations of grading the Ge concentration to match the crystal lattice of Si to the intended crystal lattice constant at the surface of the graded Si(1-x)Gex buffer layer have been developed. The current quality of SiGe buffer layers requires further improvements. Especially the intensity of the cross-hatch for higher Ge concentrations is a major challenge.
Thus far, however, little attention has been given to the reactions after the deposition has ended. Typically the deposition is done by heating the substrate, e.g. a silicon wafer, to a certain temperature and then providing the components for growing a film in the gas phase (CVD, PVD, MBE etc.). When the film growth ends the film is fully or partially relaxed with regard to the substrate. Sometimes annealing steps are applied to fully relax the SiGe buffer. After the deposition is completed the cooling of the layered wafer starts. Because of the difference in thermal expansion coefficient between the heteroepitaxial layer and the substrate, a stress is generated, and the wafer bends to a certain degree resulting in a curvature of the wafer. The bowing of the wafer is a function of the film stress, the thickness of the film and the mechanical properties of the substrate. Attempts have been made to minimize the bow of the resulting SiGe/Si structure, for example by limiting the thickness of the heteroepitaxial layer and using intermediate layers within the SiGe buffer layer.
US2008/0017952 A1, which is incorporated in its entirety by reference herewith, describes a method to reduce bow caused by relaxed SiGe buffer layers by means of inserting thin strained transitional layers of silicon into the growing SiGe layer. These layers are claimed to reduce bow to a certain extent and the density of TD to less than 104 cm−2. Although this approach has some positive effect on bow, it fails in regard of reducing cross-hatch and surface-roughening.
Controlling the shape of a wafer by using front and backside layers with counteracting stress components is a well known method (US 2003/033974 A1; U.S. Pat. Nos. 4,830,984; 5,562,770; GB 2,369,490; JP 05,144727). Typically, thermally mismatched layers are deposited on the backside of a wafer in order to counteract the film stress generated by front side layers.